Transceiver device

ABSTRACT

The transceiver according to the invention is a transmitting and receiving device for the transmission of digital signal sequences. Chirp signals are used for signal transmission by way of the air interface, such signals making it possible for the BT-product in the transmission band to be very much greater than the BT-product in the baseband by simultaneous frequency and time spreading. The transmitting and receiving device is distinguished in that chirp signals which are different in respect of the BT-product and/or the time-frequency characteristic can be stored in a memory in order for them to be selectively called up and raised into the transmission frequency band by direct upward conversion. No mirror frequency bands are produced with this procedure so that complicated band pass filters in the carrier frequency position can be eliminated. Direct and automatic demodulation into the baseband is also possible in the receiver, being dependent on the feasibility of the asynchronously operating dispersive filters (for example in the form of SAW components) for the carrier frequency band. As the dispersive SAW filters which can be produced at the present time in the microwave field are still of excessively low efficiency, the invention set forth herein describes receiver structures which presuppose an IF part, in which structures therefore compression of the received chirp signals is effected in the IF position. The compressed chirp signals can then be asynchronously demodulated into the baseband by rectification or, when using convolution pulses, by multiplication. The transmitting and receiving device according to the invention is distinguished by remarkable robustness and resistance in relation to narrow-band and wide-band interference signals. The overall system belongs to the class of matched filter systems.

The invention relates to a transmitting-receiving device, referred to asa transceiver, which is suitable within a transmission system both forproducing and emitting and also for receiving and processing chirpsignals.

With the transceiver according to the invention chirp signals orcombinations of chirp signals of differing configuration are producedand emitted and likewise different chirp signals or combinations ofchirp signals are received and processed.

Processes for producing chirp signals are well known from the art. Thusfor example in the radar art dispersive delay lines are in the form ofsurface acoustic wave filters (SAW), such that, after excitation with asignal pulse, they produce a corresponding chirp signal, that is to saya downchirp signal or an upchirp signal.

Generally the transceivers also include suitable receiving devices whichreceive the upchirp or downchirp signals and in turn subject them tofurther processing in circuits, wherein a received upchirp can be forexample a logic zero and a received downchirp can be a logic one in thesense of digital technology. Once again suitably configured SAW filtersserve to receive the chirp signals.

Hitherto, when various chirp signals are to be produced in such atransceiver, a correspondingly large number of SAW components also hadto be provided as only one given chirp signal characteristic can beproduced per SAW filter. For a change in the chirp characteristic, it isthen basically necessary to switch over to the respectively required SAWfilter, and wide-band analogue switches are used for that purpose. Thedesired flexibility is achieved at the cost of a very high level ofcircuitry expenditure.

In accordance with the presentday state of the art dispersive SAWfilters cannot be produced for just any high frequency ranges. Thereforethe chirp signals generally have to be produced in the IF-position andthen converted with modulation devices into the transmission frequencyband. Before emission expensive and complicated measures additionallyhave to be taken for mirror frequency suppression. The dispersive SAWfilters available at the present time in addition have a high level ofinsertion damping (for example −24 dB), the compensation of which, withsuitable wide-band amplifiers, always entails an increased currentconsumption on the part of the entire system.

A further variant of chirp signal production is tuning avoltage-controlled oscillator (VCO) with a ramp-shaped signal. Dependingon the respective characteristic of the VCO a voltage which rises in aramp configuration at the control input can produce for example anupchirp while a voltage which falls in a ramp configuration can producea downchirp. That process is in principle very simple and makes itpossible for chirp signals to be produced directly in the transmissionfrequency position. It will be noted however that problems are involvedin emitting successive chirp signals of the same characteristic, forexample a sequence of upchirp pulses. In that case the control signalhas a discontinuity at the transition from one chirp pulse to the other,whereby a switching function is superimposed on the output signal, withthe consequence that the spectrum is undesirably increased in width.That means that the chirp signal in the transmission frequency positionhas to be further subjected to band pass filtering prior to emission,with attendant expenditure and complication.

In general the ramp-shaped voltage signal at the VCO control input alsocannot be reset as quickly as may be desired so that the result is asawtooth-shaped control signal with a long ramp for chip production anda short return ramp. That in turn undesirably produces a further veryshort chip pulse with its own frequency-time characteristic, which isperceived at the receiver end as noise. Blanking out the short ramphowever again produces a switching function with the consequence ofspectral broadening of the transmission signal.

A further technically known method which in that respect can be wellintegrated is the synthetic production of any signals in an intermediatefrequency position or in the baseband. In that case sampled signalswhich are quantized at a higher stage are held in a memory and whenrequired subjected to digital/analogue conversion and converted into thetransmission frequency band. This process is advantageous in particularbecause of the possible flexibility. It can also be readily used for thesynthesis of chirp signals. The disadvantage of this method however isthat a comparatively high level of complication and expenditure in termsof digital technology and storage space is involved, particularly when,with a high degree of quantization, a relatively large number of chirpsignals of differing characteristics have to be provided. That storagerequirement and the necessity for higher-stage D/A converters howeveralways also entails an increased level of power demand in thetransmitter part of the transceiver and naturally a larger chip area ifthe situation involves integrating the transmitter functions.

To sum up it can be said that, with the previously known methods, theproduction of chirp signals of differing characteristics entails a highlevel of circuitry complication and expenditure (for example due to theprovision of a high number of different dispersive SAW filters and theassociated analogue switches in the transmitter), a high level ofcurrent consumption in the transmitter (for example to compensate forthe insertion damping in the dispersive SAW filters), expensive measuresfor mirror frequency suppression and for spectral shaping in thetransmission frequency band or an increased requirement for chip area ifcomplex digital signals such as for example higher-stage D/A convertershave to be implemented.

The problem of the invention, for producing, emitting and receivingchirp signals of differing characteristics, is to provide a transceiver,that is to say a transmitter and a receiver, which in terms of thedifferent chirp signals produced is of a simpler structure than thepreviously known transceivers, which affords the maximum level offlexibility in the choice of the chirp characteristic, which produceschirp signals or combinations of chirp signals in the transmissionfrequency band without going by way of an intermediate frequencyposition, and which does not require any spectral shaping and filtermeasures in the transmission band.

In accordance with the invention that object is attained by atransceiver having the features of claim 1. Advantageous developmentsare set forth in the appendant claims.

The transceiver according to the invention serves for producing,emitting and receiving chirp pulses. In the special case chirp pulsesare linear frequency-modulated pulses of constant amplitude of theduration T, within which the frequency progressively changes linearlybetween a lower and an upper frequency in a rising mode (upchirp) orfalling mode (downchirp). The difference between the upper and lowerfrequencies represents the band width B of the chirp pulse. The overallduration T of the pulse, multiplied by the band width B of the pulse, isreferred to as the expansion or spread factor ψ.

If a chirp pulse passes a dispersive filter of suitablefrequency-transit time characteristic then what occurs at the output ofthat filter is a carrier frequency pulse with a sin(x)/x-shaped envelopecurve—what is referred to as a compressed pulse. The peak power of thecompressed pulse is then increased in relation to the peak power of theinput chirp pulse by the factor B•T. The compression of a chirp pulse isreversible. If a carrier frequency pulse with a sin(x)/x-shaped envelopecurve of the band width B passes a dispersive filter of suitablefrequency-group transit-time characteristic, then the result is a chirppulse of equal energy, of the length T. In order therefore to convert asin(x)/x-pulse into a chirp pulse, firstly it must be impressed on acarrier oscillation and then passed to a dispersive filter. That alreadydescribes a current process for producing chirp pulses.

Communication transmission with chirp pulses can be organised in aparticularly simple situation in such a way that the symbol alphabetcomprises the two elements ‘upchirp’ and ‘downchirp’. For example anupchirp pulse would be transmitted for a logic zero while a downchirppulse would be correspondingly transmitted for a logic 1.

If the advantage of active transmission of both logic states is waived,then it is also possible to establish on/off keying with upchirp pulsesor on/off keying with downchirp pulses.

A special form of the chirp signals or the combination of chirp signalsis the convolution signal. It is produced by the simultaneous productionand superimposition of an upchirp pulse and a downchirp pulse. By virtueof the choice of a suitable phase displacement between the upchirp anddownchirp pulses it is possible for convolution signals to be generatedin such a way that, after demodulation at the receiver end, they have apositive or a negative deviation so that active transmission of the twologic states (zero and one) is also possible with convolution pulses.

The aim of the invention is to provide a transmitting-receiving devicewhich at the transmitter end produces and emits chirp signals and whichat the receiver end is capable of receiving and demodulating chirpsignals. Chirp signals were selected for communication transmission forthe reason that they have a series of advantages over other modulationsignals:

By conversion into a chirp signal, it is possible to transform a shortpulse of high peak power into a chirp pulse of equal energy but which ismuch longer, in which case the transmission power is correspondinglyreduced, for example to the allowed peak power of a power-limitedtransmission channel. That pulse is transmitted by way of thetransmission channel to the receiver and compressed there. In that caseonce again a short pulse is produced, which is increased in power inrelation to the reception pulse. Accordingly therefore, a signal of muchhigher peak power and therefore with a much greater spacing in relationto noise signals has been transmitted by way of the power-limitedchannel.

In the reverse way of looking at the situation, a chirp transmissionsignal can stand out from other transmission systems which transmit atfull signal power by way of power-limited channels, insofar as theparticular signals are chirped, that is to say transmitted at a greatlyreduced level of power, without the performance dropping off in relationto the comparative systems. Chirp transceivers therefore presentthemselves for use in environments in which a reduction in radiationloading by transmission installations (low human exposure) is animportant consideration.

Chirp signals are wide-band signals and they can be produced in such away that their spectrum completely fills an available transmissionchannel of the band width B. For that purpose, for a symbol to betransmitted, a carrier frequency pulse with a sin(x)/x-shaped envelopecurve is produced and then transformed into a chirp pulse. That carrierfrequency pulse is of a mean width □ which is determined as the inverseof the band width B. Accordingly the available channel band width Bdetermines the possible time resolution of a chirp transmission system.When preparing for chirp transmission therefore firstly pulses areproduced with the lowest possible BT-product (B•δ=1). Those pulses areconverted prior to transmission by way of the air interface into chirppulses of equal band width B but much greater duration T. In otherwords, the pulses are transmitted by way of the air interface with amuch greater BT product (B>>1). The reverse procedure takes place at thereceiver end. The incoming chirp pulses are again converted intosin(x)/x-pulses of the BT-product B•δ=1 and subjected to furtherprocessing.

The serious increase in the BT-product prior to transmission by way ofthe air interface is the real reason why chirp transmission processesare so robust in relation to disturbances in transmission. Other signaltransmission processes in which the BT-product remains the same insignal preparation at the transmitter end, during transmission and insignal processing at the receiver end, do not enjoy that advantage.

Data sequences of any symbol rate R up to the limit data rate can bereproduced on chirp pulses and transmitted using the full channel bandwidth. In regard to the situation where the symbol rate is less than theband width B, it is possible to refer to frequence spreading of thesymbol sequence to channel band width. Linked thereto is a spreadinggain which can be determined as the quotient of the band width B and thesymbol rate R.

A matched filter receiver serves to receive chirp signals. Clearly thatspreading gain can therefore be so interpreted that the transmittedchirp signal is compressed (that is to say unspread) in the receiver bymeans of an especially adapted matched filter (the dispersive delayline) while non-chirped signal components, for example superimposedinterference or noise signals, are spread in the same matched filter ofthe receiver.

The possible spread gain reaches a maximum when the symbol duration 1/Ris equal to the chirp duration T. It becomes minimum when the symbolrate R is equal to the chirp band width B.

If when chirping a sequence of symbols the symbol duration 1/R is lessthan the chirp duration T, then each individual symbol experiences aspread in respect of time beyond its symbol limits. A chirp pulse isproduced for each symbol, with the chirp pulse being longer than thesymbol itself. Then, a sequence of chirp pulses which are superimposedand overlap in respect of time occurs at the output of the dispersivefilter.

The spread in respect of time of the symbols can be determined by thequotient of the chirp duration T and the symbol duration 1/R. It reachesits maximum when the symbol rate R and the chirp band width B are thesame.

The spread in respect of time of the symbols involves a furthertransmission advantage which becomes particularly effective at high datarates. The time spread of the symbol to the much greater length T meansthat the symbol energy of each symbol is distributed along the time axisover a correspondingly greater range.

If disturbances and in particular short-term interferences occur insignal transmission, then it is possible to use the time-spreadtransmission for interference suppression. It may be assumed that thetransmitter emits time-spread symbols (in the example, chirp pulses),wherein superimposed thereon on the transmission path are wide-bandinterference pulses (for example quasi-Diracime pulses). The signalmixture of chirp pulses and interference pulses passes at the receiverinput a dispersive filter (chirp filter) which implements compression ofthe chirp pulses into sin(x)/x-pulses. All non-correlated signalcomponents, that is to say which are not present in the form of chirppulses, are in that situation spread in respect of time. Theirinterference energy is distributed over a greater period of time, thatis to say over a plurality of adjacent symbols. The probability that anindividual symbol is destroyed by such an interference pulse is reduced.The bit error rate in transmission also falls at the same time.

In summary it can be said that chirp signals for data transmission overwide-band and interference-affected communication channels afford aseries of advantages which predestine them for use in the transceiveraccording to the invention.

A technically well-known variant of the synthesis of transmissionsignals which is wide-spread for example in software radio systems isthe digital production of signals in an intermediate frequency position.That process also presents itself for the representation of chirpsignals.

In that case the sampled and quantized chirp signal is stored in amemory, for example an ROM, in the IF-position. To produce a chirp pulsethe stored chirp sequence is passed to a digital/analogue converter, atthe output of which the analogue chirp signal can be taken off. Byvirtue of the high sampling rates necessary that method can only beconsidered for the lower frequency positions (low IF). Conversion intocommon transmission frequency positions, for example in the ISM band,always still requires suitable upward mixers and associated filtermeasures for mirror frequency suppression. In accordance with the statedobject of the invention however, for reasons of simplicity, the aim isto forego spectral filtration procedures, mirror frequency suppressionand band restriction in the transmission frequency band. In addition theaim is to provide for the simplest possible structure for thetransmission device and the maximum level of flexibility in terms ofselecting the transmission signals.

In accordance with the invention therefore the storage of the complexchirp signal in the baseband offers a better way. For that purpose thereal part and the imaginary part of the provided chirp baseband signalare sampled, quantized and stored as independent bit sequences in thememory (for example an RAM or an ROM). In the baseband part of thetransceiver the stored baseband sequences can be read out upon beingfetched and can be converted into a chirp signal in a transmissionfrequency position.

FIG. 1 illustrates a transmission device by way of example. FIG. 2 showsthe signals occurring at the various points in the arrangement.

Different chirp baseband signals are separately stored in accordancewith the real part and the imaginary part in a memory (see FIG. 1) asbit sequences (sequence 1, sequence 2, . . . ). The selected chirpsequence pair in question is addressed by way of the block ‘Addressing’which is connected for example to a digital data source. FIG. 2 a showsby way of example three information symbols (LOW; HIGH; LOW) of adigital data source, which are to be transmitted.

For each of those symbols, two bit sequences (sequence_I and sequence_Q)are read out by way of the block ‘Addressing’ (FIG. 1), by way of areading-out device, for example a parallel/series converter. At theoutput of the parallel/series converter are the two bit sequences g2 andg3 (see FIGS. 2 b and 2 c) which are passed to the inputs ofdigital/analogue converters (DAC). The D/A-converted signals arefiltered with the two low pass filters (TP) in the baseband. The signalsg4 and g5 occurring at the output of the low pass filters (see FIGS. 2 dand 2 e) are transferred by means of a suitable modulation device (forexample an I/Q-modulator) directly into the desired transmission band.The chirp signal g6 (see FIG. 2 f) at the output of the I/Q-modulatordoes not contain any mirror frequencies so that it can be emitted in thetransmission frequency position without further filter measures.

It is a particular advantage of this process that chirp signals of anycharacteristic (for example upchirps, downchirps or chirp signals with adiffering BT-product and a differing characteristic) can be stored inthe memory, and with sufficient memory space they can be selectivelyfetched so that, depending on the requirements involved in transmission,it is possible to have recourse to one of the stored chirp signals orthe other. It can also be envisaged that the required chirp sequences,in the procedure involved in starting operation or initialising, aretransferred into the memory by way of a download, but if required canalso be replaced by re-programming. Accordingly the transceiver has aprogrammable transmission part which makes it possible to select thetransmission signals with the highest possible level of flexibility andto emit them without changes to the hardware (see FIG. 1).

Some parameters are necessary for digital storage of a chirp signal, notleast for estimating the memory requirement. They include initially thesample rate (chirp sample rate). It is dependent on the band width ofthe chirp signal, its minimum value is determined by the samplingtheorem.

There is a greater degree of freedom in regard to establishingquantization. It can be shown that, with an arrangement as illustratedin FIG. 1, it is readily possible to produce chirp signals if theselected quantization of the pre-stored sequences has an only very lownumber of stages.

The proposed process makes it possible for bit quantization to be freelyselected in the range of 1, 2, 3 . . . n bits. In other words, in thesimplest case of 1 bit quantization frequencies of the digital symbols‘0’ and ‘1’ are sufficient, for representation of a chirp signal in thebaseband. In that particular case the connected circuit is furthersimplified by virtue of the digital/analogue converters becomingsuperfluous. As a distinction from known processes for signal synthesisin the baseband, the transceiver according to the invention (as shown inFIG. 1) can synthesize the transmission signal from two stored binarysequences without additional digital/analogue converters.

In all other cases digital/analogue converters of the appropriate orderare employed.

In a particular implementation of the invention convolution signals areused for transmission purposes. For the production of convolutionsignals upchirp and downchirp signals are superimposed in a given mannerin such a way that the resulting signal is purely real. Therefore only areal part has to be stored in the baseband. Thus, for direct modulationpurposes, D/A-conversion in only one channel is sufficient, with asimple modulation device (for example a mixer or a modulator) with areal carrier signal. This means that the complication and expenditurefor storage of the signals and for the modulation thereof into thetransmission frequency band is halved.

As shown in FIG. 1 the two D/A-converters (DAC) are followed by suitablelow pass filters (LP), the function of which is to limit the spectrum inthe baseband to the desired band width. In the case of 1 bitquantization spectral limitation must be effected solely by those lowpass filters, optionally higher-grade filters have to be used.

With higher levels of quantization the sampled and quantized basebandsignals can already be weighted prior to storage in the memory withselectable filter functions (for example with a cosine roll-offcharacteristic) so that the chirp frequencies which are fetched in thetransmission situation already satisfy simple requirements in terms ofspectral purity of the baseband signals. That reduces the level of thedemands on the downstream-connected low pass filters. It can also beenvisaged that this baseband pre-filtering already completely satisfiesthe spectral demands on the chirp signal so that further filter stagesare no longer necessary. If it is assumed that a higher-stage level ofquantization is specifically selected for that purpose in order toimplement additional baseband filtering of that kind, it is thenpossible to talk of exchanging quantization complication and expenditure(memory requirement, expenditure for digital part and A/D-converter),for the complication and expenditure for implementation of the low passfilter stages.

An embodiment by way of example for the described production of chirpsignals is shown in FIG. 2 g.

The embodiment of FIG. 2 g describes the production of chirp signals ofvarying characteristic in the ISM band at 2.44 GHz and with a symbolduration of 1 μs.

In a frequency divider firstly the carrier frequency TX 2441.75 MHz isdivided down to 244.175 MHz by way of a two-stage frequency divider withthe factor 10:1. The frequency produced in that way corresponds to thesample rate with which the chirp signals are to be synthesized in thebaseband. Accordingly 244 samples have to be coded within the symbolduration of 1 μs. As the read-out speed of conventional memories(RAM/ROM) is generally too low for them to be read out at that rate, amemory is used, which is operated at half the sample rate, but which inreturn has double the data bus width. Therefore the frequency TX 244.175MHz is divided down once again by the factor of 2 to 122.0875 MHz. Thesequencer (SEQ) and the memory are operated with that clock. Thenecessary address space of the memory is determined as a quarter of thelength of the chirp sample rate. The data bus width can be determined asthe product of the number of quantization stages (in bits) and thefactor of 4. The sequences IROM and QROM are stored in the memory.

As the chirp sequence is center-symmetrical, only half of the sequenceis stored. In the reading-out operation the complete sequence isproduced by counting up the address value and then counting down in thesequencer (SEQ).

The multiplexer (MUX) which is connected to the memory componentserialises the data words which are placed in mutually juxtaposedrelationship in the memory. The databus from the memory component ismultiplexed to a databus which is of half such a width. In that case thedata rate of the bit sequences which are read out of the memory isdoubled.

For the production of upchirp, downchirp and convolution pulses orsymbols in the upchirp QPSK mode or in the downchirp QPSK mode theincoming IROM and QROM data streams are logically linked in theadjoining block MAP (see the Table), thus giving the desired symbols.The selection of symbols is effected by way of a 4-bit data word MD.Accordingly, with only two pre-stored bit sequences, it is possible tosynthesize all specified symbols of the various chirp modes ofoperation.

The two bit sequences for I and Q are converted into analogue signals bymeans of two D/A converters and subjected to band restriction with theconnected low pass filters (in the example leapfrog filters). The outputsignals of the low pass filters are then converted into the transmissionfrequency band with an I/Q-modulator.

The chirp transmission system which is subject-matter of this inventionbasically permits direct compression and demodulation of the incomingchirp signals into the baseband on the receiver side. As however theimplementation of suitable dispersive filters for the transmissionfrequency bands which are common nowadays also encounters considerabletechnical difficulties, in the present invention each of the illustratedreceiver variants is provided with an input stage for conversion of thereception signal into the intermediate frequency position. If dispersivefilters can also be embodied in the foreseeable future in the desiredhigher carrier frequency positions, then the IF-stage can becorrespondingly omitted without the rest of the receiver structuresaccording to the invention being affected thereby.

For processing incoming chirp signals the transceiver according to theinvention firstly includes at the receiver end a conversion device(mixer, downconverter) which converts the incoming signals into theintermediate frequency position. The intermediate frequency signal isthen passed to the inputs of two complementary dispersive delay lineswhich must be matched in terms of their frequency-group transit timecharacteristic to the chirp signal characteristic of the transmitter.The compressed pulses which occur at the outputs of the dispersivefilters are demodulated with suitable detector circuits into thebaseband, there converted with threshold value comparators into datapulses which can be processed in the adjoining digital evaluationcircuits of the receiver.

While the characteristic of the chirp signals which are produced at thetransmitter end can be easily programmed and also changed, the receivingdevice is dependent on the use of dispersive filters (for example SAWfilters), that is to say the provision of various hardware components.As however, with the exception of the dispersive filters, all thereceiver hardware remains unchanged, the receiver can also be easilytuned to a newly selected transmission chirp signal, for example uponadjustment or in service procedures. If for example the dispersivefilters are pluggably connected to the receiving device and can beeasily exchanged, it is then possible for good reason to also talk ofhardware programming of the receiver part.

The transmitting device and the receiving device of the transceiveraccording to the invention can therefore be conveniently programmed forthe transmission of chirp signals of selectable chirp characteristics.

One of the operating modes of the described transceiver is datatransmission by means of convolution pulses. The particular advantage ofthis mode of operation is the small amount of memory required forstoring the chirp sequences and the simple hardware structure of thetransmitting part.

A convolution pulse is produced by the superimposition of an upchirppulse and a downchirp pulse which is produced at the same time.Convolution signals can be so generated by the choice of a suitablephase displacement between the upchirp and downchirp pulses that thecarrier frequency pulses which occur after compression at the receiverend in complementary dispersive filters admittedly always involve thesame envelope curve, but in the case of the ‘positive’ convolutionpulses they have the same carrier phase and in the case of the‘negative’ convolution pulses they have a phase displacement of 180°.

Convolution pulses are particularly easy to demodulate in the receiver.In principle there is the possibility of implementing directdemodulation from the transmission frequency band into the baseband. Inthat case upchirp and downchirp components can be separated again bycomplementary dispersive filters with a suitable frequency/transit timecharacteristic. A compressed upchirp pulse occurs at the output of theone delay line while a compressed downchirp pulse occurs at the outputof the complementary delay line. Coherent demodulation into the basebandis achieved by simple multiplication of the two compressed signals. Thepulse shape corresponds to a squared sin(x)/x pulse, with positivedeflection in the case of a transmitted positive convolution pulse andwith negative deflection in the case of a negative convolution pulse.

It will be noted however that the described direct demodulation ofconvolution signals into the baseband presupposes the presence ofdispersive filters for operation in the transmission frequency position(for example in the ISM band around 2.4 GHz). As long as those filtersstill cannot be produced or can be produced only at disproportionatelyhigh cost demodulation can be effected only after converting thereception signal into the IF-position.

The prerequisite for successful demodulation of the convolution pulsesin the receiver is the best possible congruence of the envelope curvesof the compressed pulses in the receiver.

That congruence can occur only when the center frequency of the receivedsignal which is mixed down into the IF-position coincides as well aspossible with the center frequency of the two complementary dispersivedelay lines.

In the case of conventional quartz stabilisation of transmitting andreceiving LO however such a high frequency displacement can alreadyoccur that the demodulation of convolution pulses becomes animpossibility. Because of the complementary frequency-group transit timecharacteristic of the delay lines the envelope curves of the twocompressed pulses then move away from each other on the time axis.

That therefore entails the necessity for carrier recovery from thereceived chirp signal. As demodulation of the convolution signals occursnot in the baseband but in the IF-position, a local oscillator must beproduced, the frequency of which is the difference of the recoveredcarrier frequency and the known center frequency of the delay lines(that is to say the intermediate frequency used).

As in the received chirp signal the carrier frequency (center frequency)is only one of many frequency components and is in no way distinguishedin relation to the others, only methods which can extract the carrierfrom a pure double-side band signal fall to be considered for carrierrecovery.

In this connection the literature [K D Kammeyer: Nachrichtenübertragungpages 424-428, 2nd Edition 1996, Teubner Stuttgart] discloses principleswhich are based on frequency multiplication of phase-modulated receptionsignals. Taking the resulting frequency mixture the n-times carrierfrequency can then be subjected to narrow-band filtering out and can bedivided down and the desired reference carrier is produced by means of aphase regulating circuit. What is common to those processes is that,depending on the state number n of phase modulation the reception signalmust be squared (Id n)-times in order to derive the n-times carrierfrequency.

The disadvantage of these methods is that multiple product formation ofthe reception signal can only be implemented at a very high level oftechnical complication and expenditure, and in the case of commontransmission bands (for example the ISM band) the frequencies which areproduced in that case rapidly attain such a level that processing (forexample dividing down) in phase regulating circuits can only beimplemented with difficulty. In addition there is another importantreason against the use of those processes. It is not possible to specifya limited number of phase states for chirp signals, and squaring of thereception signal therefore must theoretically take place infinitelyoften in order to arrive at an evaluatable carrier frequency.

A further technically common method of carrier recovery is use of aCostas regulating loop. Carrier regulation with the Costas loop is basedon the received signal being converted into the baseband by means of anI/Q-demodulator, the demodulator output signals being subjected to lowpass filtering and then being multiplied together in order in that wayto obtain a regulating criterion for the phase of the reference carrier.The VCO which produces the reference frequency can be actuated directlywith the product signal.

That process is not suitable for carrier regulation in chirptransmission systems as the demodulated signals in the baseband are notconstant but chirped signals, with a completely different phaseconfiguration, so that it is not possible to draw any conclusions aboutthe phase of the reference carrier, from a phase comparison.

The previously known carrier recovery processes are evidently unsuitablefor use in the transmission of convolution signals.

What is involved is finding a process which can be applied to chirptransmission processes and which produces and stabilises a localoscillator in such a way that convolution pulses can be received andreliably demodulated.

That requirement is met by an arrangement as set forth in claim 20.

That arrangement is illustrated by way of example in FIG. 3.

This involves a receiving device which firstly converts the incoming RFreception signal into a suitable IF position with a conversion device,for example a mixer, and then feeds it to the inputs of dispersive delaylines with a complementary frequency-group transit time characteristic.The output signals of the delay lines are demodulated into the basebandwith detector stages and then converted into rectangular pulses withthreshold value comparators. Those rectangular pulses are passed to aphase detector which is followed by a regulator. The output signalthereof influences a voltage-controlled oscillator (VCO) with which thelocal oscillator (LO) of the system is produced.

If convolution pulses occur at the receiver input, then compressed chirppulses are produced at the outputs of the complementary delay lines, thetime displacement of the chirp pulses representing a measurement inrespect of the deviation of the IF center frequency from the centerfrequency of the delay lines, and which can be used as a regulatingcriterion for the frequency of the reference carrier (LO).

The phase detector checks for congruence of the demodulated compressedpulses, its output voltage varies in respect of magnitude and polaritydepending on the respective established time displacement of the pulses.The subsequent regulator changes the setting voltage of the VCO untilthe envelope curves of the compressed chirp pulses lie one above theother. The regulating circuit is latched and the prerequisite formultiplicative demodulation of the convolution signals applies.

Accordingly frequency synchronisation does not take place as is usual inthe known processes between the carrier frequency of the receptionsignal and the reference carrier (LO), but between the IF signal and thecharacteristic of the dispersive filters. The system is not synchronisedto a received carrier signal but conversely it synchronises the receivedsignal to a system-specific reference, the center frequency of thecomplementary dispersive group transit time filters.

The incoming signal is shifted in frequency into the IF position to suchan extent until its center frequency and the center frequency of thedispersive filters lie one above the other. In other words, in a simplefashion, the system also regulates out changes in the filter centerfrequency due to a rise in temperature, ageing or other influences.

In order to synchronise the receiver device, a data sequence can bepreceded by a preamble of convolution pulses which serves specificallyfor bringing the frequency regulating circuit into effect. Thesynchronisation attained is maintained even upon the subsequenttransmission of the data pulses, in that respect it is immaterialwhether positive or negative convolution pulses or prolonged sequencesof the same polarity are received. If convolution pulses occurring inburst-wise manner are received with the illustrated receiverarrangement, then a preamble must again precede each data burst, forsynchronisation purposes.

In a specific configuration of the invention a preamble of convolutionpulses is firstly transmitted prior to the transmission of a data burst,and upon the attainment of the latched state the VCO setting voltage issampled with a sample-and-hold member and held fast for the duration ofthe data burst.

The structure of the receiver device (see FIG. 3) permits both thereception of convolution signals and also the reception of simple chirpsignals (for example upchirp/downchirp). The described regulatingcircuit can be switched off for the latter case. It is then sufficientto use a simple PLL circuit with a quartz reference for producing thelocal oscillator.

In a further implementation of the invention a data sequence whichcomprises upchirp pulses (logic HIGH) and downchirp pulses (logic LOW)is preceded by a preamble of convolution pulses which serves forfrequency synchronisation, after latching of the frequency regulatingcircuit the VCO setting voltage is sampled and held fast for theduration of the data burst. In that case there is no need to provide anyadditional quartz-stabilised PLL circuit for producing the localoscillator, for the reception of simple chirp signals.

A further implementation of the invention is automatic frequencyregulation for an upchirp/downchirp-transmission system, shown by way ofexample in FIG. 4. In this case, in a preamble, a series of mutuallyalternate upchirp and downchirp pulses are transmitted. Rectangularpulses then appear in the symbol clock at the inputs of the phasedetector, those rectangular pulses being displaced in respect of timefrom one input to another. In the steady-state condition, that is to saywhen synchronisation has been achieved, that displacement is preciselyhalf a symbol period, that is to say 180°. For that situation the phasedetector is so designed that its output signal in terms of magnitude andpolarity reflects the instantaneous phase shift and accordinglydisappears in the latched condition. The frequency regulating circuitshown in FIG. 4 can then also be used for frequency regulation ofup/down chirp systems. Initially that only applies for the precedingpreamble. For the duration of the subsequent data sequence the VCO inputsignal must be clamped again at the voltage value of the latchedcondition.

For transmission systems which are used selectively for the transmissionof up/down chirp signals or convolution signals, the phase detector canthen be adapted to be switchable so that both transmission modes canoperate with the same frequency regulating circuit.

The described frequency regulation can only be used for up/down chirptransmission systems if upchirp and downchirp symbols are receivedalternately at least until latching occurs, for example within apreamble which precedes the data burst. The subsequent data signal isgenerally characterised by the irregular succession of upchirp signals(for example logic HIGH) and downchirp signals (in the examplecorrespondingly being logic LOW). That also includes prolonged pulsesequences of the same polarity.

In the case of a known symbol period however it is possible for themissing symbols to be inserted as dummy symbols in two branches betweentwo symbols of the same polarity which are displaced in respect of timeby more than one period. In FIG. 4 for that purpose a block ‘RestoreSequence’ precedes the phase detector. The uninterrupted symbolsequences which are thus produced in both branches are then fed to thephase detector, the rest of the regulating circuit operates in the knownmanner. The prerequisite for this process is that the time spacings ofsimilar symbols do not turn out to be too high. In order to ensure this,the symbol sequences can be suitably scrambled in the transmitter priorto the transmission, with the aim of the number of successive symbols ofthe same polarity not exceeding a fixed value k.

If the up/down chirp transmission system has a receiver as shown in FIG.4, then frequency synchronisation which is achieved within a preamblecan also be maintained during the subsequent transmission of datasequences of any length.

The transmission of digital data sequences presupposes on the receiverend not only frequency synchronisation but generally also clocksynchronisation. That involves deriving the symbol clock from thereception signal in correct phase and frequency relationship.Technically common processes are clock derivation with synchronousdemodulator for frequency-modulated signals or clock recovery from thedemodulated baseband signals, in which the baseband signals which havebeen subjected to low pass filtering are summed and then the clockfrequency is filtered out of the sum signal with a band pass filter.Still other processes provide a specific PLL circuit for clock recovery.

What is common to those processes is that they can only be embodied at arelatively high level of circuitry complication and expenditure. For anintegrated transceiver circuit, the functionality of which is to beensured with the lowest possible power consumption and the smallestpossible requirement in terms of chip area, such complicated structurescannot be considered for clock recovery. The task was that of finding asolution for clock derivation, which is founded on the existingstructures for chirp signal reception, which arises functionallydirectly out of chirp signal demodulation and which permits securereconstruction of the system clock at minimal additional complicationand expenditure.

That object is attained by a transceiver as set forth in claim 32.

It is possible with the transceiver according to the invention to senddata sequences comprising upchirp/downchirp pulses or data sequences ofconvolution pulses and to asynchronously demodulate same at the receiverend.

FIG. 5 represents a receiver device for up/down chirp transmission withsubsequent clock derivation.

The chirp signals which come in at the receiver input are firstlyconverted into the IF position, automatically and asynchronouslycompressed with complementary dispersive delay lines and demodulatedinto the baseband with detector circuits.

The rectangular pulses which occur at the outputs of the subsequentthreshold value comparators only still have to be linked together by asuitable logic member (for example an EXCLUSIVE OR gate) in order toderive the symbol clock. The symbol clock (CLOCK) is fed to the clockinput of a jK flip-flop, the inputs j and K are suitably connected tothe comparator outputs. In that way the output Q (DATUM) of theflip-flop is set with each clock pulse to the current logic state (forexample upchirp=LOW and downchirp=HIGH), for the duration of a period.

The particular advantage of the illustrated process for asynchronouslyderiving the symbol clock is that the receiver device directly followsevery change, at the transmitter end, in the symbol rate and thus thesymbol clock without special switching-over procedures orre-initialisation procedures being required in the receiver. This forthe first time permits a flexible and a fluid variation in the data rateof a transmission system.

In the situation involving the transmission of convolution pulses thesymbol clock, presupposing that frequency regulation is in thesteady-state condition, can in principle be derived in the same manner.

FIG. 6 shows a receiving device for convolution pulse transmission.

The input circuit of the receiving device again comprises a converterand the two dispersive filters. For demodulation of the convolutionpulses themselves, the output signals of the two delay lines aredirectly multiplied by each other, resulting in a bipolar basebandsignal. A variant for deriving the symbol clock is full-waverectification of that baseband signal and subsequent evaluation with athreshold value comparator. The output signal thereof also carries thesymbol clock (CLOCK).

A further variant for clock derivation in respect of convolution pulsesis shown in FIG. 7.

This circuit makes use of the fact that, upon the reception ofconvolution pulses and in the steady-state condition of frequencyregulation, the comparator output signals in the two branches equallycarry the symbol clock so that, in regard to clock derivation, it ispossible to restrict the system to one of the branches. In order toincrease security in terms of interference, it is advantageous for thetwo comparator output signals to be linked by way of a logic AND member.The system clock (CLOCK) occurs at the output of that AND member.

A further variant for clock derivation in respect of convolution pulsesis shown in FIG. 8.

FIG. 8 firstly shows the input circuit for the demodulation ofconvolution pulses (mixer, dispersive filters, multiplier). Theprerequisite for clock derivation in the illustrated receiving device isthe steady-state condition of frequency regulation.

For demodulation of the convolution pulses themselves the output signalsof both delay lines are directly multiplied by each other, this giving abipolar baseband signal. That signal is compared at two threshold valuecomparators to a respective positive and a negative threshold value. Theoutput signals of the comparators are linked together by way of a logicOR member in order to derive the system clock (CLOCK). The current datumcan be suitably taken off at the output Q of the jK flip-flop.

The transceiver according to the invention makes it possible toimplement gating of the comparator output signals at the receiver end inboth modes of operation. That gating is directed to the operatingsituation with a symbol rate which is fixed or which is known to thereceiver. The arrangement is further assumed to involve a circuitportion for clock derivation.

FIG. 9 shows a variant of the gating, which is used in the transceiver.FIG. 10 shows the associated signals, by way of example.

FIG. 9 is a diagrammatic view which firstly shows a switch which isactuated by way of the block ‘Time control’. The CLOCK signal g8 hasbeen produced in an upstream stage for clock derivation. The switch isopened and closed with the signal g9. As shown in FIG. 10 the switch isinitially closed in the rest position. The first incoming symbol clockpulse is recognised by the time control and, after a short time delay(controlled by way of the signal g9), triggers opening of the switch andthus the blocking of further pulses which are within a given intervalwhich is less than a symbol period. After the end of the blockinginterval the switch is closed again. The next (expected) symbol clockpulse can pass and again triggers off the blocking effect.

The advantage of this arrangement is that interference pulses whichoccur within a symbol interval are suppressed. That variant isparticularly suitable for initial oscillation of the signal. If aninterference pulse undesirably first triggers off the blocking effectfor example after activation of the system, then the gate is alreadyopened again after a time which is shorter than a clock period. Thesystem does not remain in the blocked condition and can already processthe arriving symbol clock pulse.

FIG. 11 shows an embodiment of this arrangement.

In this case a logic AND member takes over the function of the switchand a monoflop determines the length of the blocking interval.

A particular implementation of the gating according to the inventionprovides for using a blocking interval of variable length. The blockinginterval can be particularly short for example in the phase involvingproducing a transient response on the part of the receiving device,while in the steady-state condition the arrangement can be switched overto a longer blocking interval which in the extreme case is only a littleshorter than the symbol duration itself.

A further implementation provides that a symbol clock pulse closes thegate for the duration of a blocking interval, and then opens it for theduration of an opening interval (within which the next symbol clockpulse is expected) and then closes it again for the duration of ablocking interval—a procedure which is continuously repeated. Thatvariant is suitable for operation in the steady-state condition.

When a chirp pulse is received by the receiving device of thetransceiver, converted into the IF position and fed to complementarydispersive filters, then not only does a compressed pulse occur at theoutput of one of the two filters, but in addition an expanded chirppulse also occurs at the respective complementary chirp filter. Theexpanded chirp pulses appear in each of the two branches assystem-specific interference signals which have to be taken into accountin terms of detection and subsequent discrimination. After demodulationinto the baseband the detected signals are compared to a threshold valuein each path. The described effect requires that the threshold value ofthe comparator is always in the region between the peak values of theexpanded pulse and the compressed pulse. That already limits thedynamics of signal detection. In addition the receiving system shouldalso be capable of reacting to changes in power at the detector input.Those changes in power involve the expanded and the compressed signalequally and result in fluctuations in amplitude of the detected signal.If operation is effected with a fixed threshold value, then thedetection limits are very rapidly encountered when the amplitude of theincoming signals changes.

That therefore involved finding a device for determining the thresholdvalues, which on the one hand is tuned to the characteristics of chirpsignal reception but which on the other hand can also react to changesin power of the input signal.

According to the invention that object is attained by an arrangement asset forth in claim 41.

FIG. 12 shows a receiving device according to the invention.

The incoming reception signal is firstly converted into the IF positionand passed to the inputs of two complementary dispersive filters. Thecompressed chirp pulses at the output of each of the two filters arepassed in both branches to an envelope curve detector, an averagedetector and a peak detector. A threshold value for the subsequentcomparator is derived from the output signals of the average detectorand the peak detector. The threshold value can variably assume any valuebetween the peak value and the average value of the detected signal. Ina particular configuration of the invention the position of thethreshold value is digitally controllable, within that interval. Theoutput signals of the envelope curve detectors are compared to thethreshold values produced in that way in both branches. The signalsCOMP_UP and COMP_DOWN are ready for digital further processing at theoutputs of the two comparators.

In the situation where no reception signals occur the threshold valuecomparator must afford the highest possible level of sensitivity but thebackground noise of the receiver device may not result in switching ofthe comparator. Therefore in a particular configuration of the inventionthe lower limit of the threshold value is so established that thethreshold value, in the rest condition (in the condition of readinessfor reception), is always higher than the detection signal of thebackground noise of the receiver device. For that purpose a voltageU_min is added to the threshold value formed from the average value andthe peak value in both branches, thereby providing that the thresholdvalue at the comparator input is always higher than the noise amplitudeat the detector output.

In summary it can be said that the transceiver with the combinationaccording to the invention of detector and comparator with adaptivethreshold establishes the threshold values in respect of amplitudediscrimination in such a way that, even in the event of power changes inthe signal at the detector input, reliable detection of complementarychirp signals is possible.

The NANONET-transceiver, the block circuit diagram of which is shown inFIG. 14, is represented in the variant which is advantageous here as ahighly integrated circuit which is provided for the transmission ofdigital data sequences and which in a very small space includes acomplete transmitter (from the digital input to the RF power amplifier),a complete analogue receiver (from the antenna input to the output forthe demodulated and digitised reception data), a programmable analoguecontrol device and a programmable digital control device.

The analogue control device comprises power management, analogue/digitalconverters, current sources, battery charge monitoring, alarm signallingand other components. All essential functions of that functional blockcan be initialised and controlled by the application software.

The programmable digital control device which communicates with externalmicrocontrollers by way of a serial periphery interface (SPI) providesvarious control functions for the analogue part of the IC. In additionthat block already performs important functions of the protocol stack asfar as the MAC layer, error correction, real time clock, wake-upmanagement, interrupt requests, automatic production of acknowledgesignals and further tasks. All functions of that block are initialisedand controlled by way of the application software on an externalmicrocontroller.

A brief description of the block circuit diagram of FIG. 14 is set outhereinafter.

Transmitter (TX):

An important situation of use for the NANONET transceiver is recordinganalogue sensor data, converting same into digital signals andtransmitting those digital data to a receiver by way of an airinterface. The Analogue Sensor Interface (1) serves for recording thesensor data in a plurality of channels, in addition that module providesa current source for supplying the connected sensors. The operation ofreading out the connected sensors is started by the applicationsoftware, the sensor data are subjected to A/D conversion by theAnalogue Sensor Interface and transmitted to the block Control Registers(x) of the digital part. The sensor data can be transmitted to theapplication by way of the illustrated linesDiIO1, . . . DiO4.

The core part of the transmitter portion is the I/Q modulator (2). Independence on the selected transmission mode the digital symbols to betransmitted are reproduced in the block Pulse Sequence (3) on topre-stored bit sequences which represent the real part and the imaginarypart of the transmission signal in the baseband. Those bit sequences areband-limited with the low pass filters (3) and (4) and passed to theinputs of the I/Q modulator (2). The carrier signal for the I/Qmodulator is produced in the block Frequency Synthesization (5). Thatfrequency synthesizer selectively produces the carrier for directmodulation at the transmitter side into the transmission frequency bandor the carrier for down-mixing at the receiver end into the IF-position.The analogue switch (6) is controlled by the signal RX/TX and effectsswitching-over of the carrier between transmission and reception modes.

The output signal from the I/Q modulator (2) is passed to apre-amplifier stage (7) and then to the Power Amplifier (8). The outputpower of the power amplifier can be controlled by the digital part byway of the block Power Control (9). The power amplifier can be switchedoff for the duration of the receiving period by way of the signal RX/TX.

Also shown in the block circuit diagram at the transmitter side is aninternal oscillator OSC (10), provided for the connection of an externalquartz, and Battery Management (11) for monitoring the charge conditionof the battery.

Receiver (RX):

The reception signal of a connected antenna is coupled into the LowNoise Amplifier (LNA) (12). The LNA can be switched off for the durationof the transmission period with the signal RX/TX. Its gain is controlledby the block AGC (13). The LNA is followed by the Downmixer (14) whichconverts the received signal into the intermediate frequency position.The subsequently connected amplifier (15), like the LNA, is incorporatedinto the automatic gain control (AGC). Its output signal is coupled outof the transceiver.

The circuit is so provided that an SAW component can be externallydirectly connected to the IF amplifier (15), the SAW componentcomprising two dispersive delay lines with a complementary group transittime characteristic. The output signals of the two delay lines arecoupled into the IC at the inputs of the amplifiers (16) and (17) whichare regulated in multi-stage fashion.

For demodulation of those signals into the baseband, a respectivedetector stage (18) and (19) and subsequently connected low pass filter(20) and (21) are respectively connected to the input amplifiers (16)and (17) in the circuit.

The two low pass filters are each followed by a respective thresholdvalue comparator (22) and (23) respectively. The threshold values forboth comparators are adaptive and are determined in the block Threshold(24) from the LP-output signals themselves.

The comparator output signals are subjected to further processing in thedigital part, there initially in the Bit Decoder.

For the demodulation of convolution pulses a multiplier (25) isavailable in the receiving part, with which multiplier the outputsignals of the dispersive filters are multiplied. The multiplier isfollowed by an amplifier stage (26) and two threshold value detectors(27) and (28) for the detection of the bipolar convolution signals. Thethreshold values for both comparators are adaptively determined withinthe block Threshold (24).

The output signals of the two comparators are subjected to furtherprocessing in the digital part.

The microcontroller interface (29) serves for transmission of thetransmission and reception data and items of control information betweenthe external microcontroller and the transceiver chip. It furthersynchronises the data communication between the two components.

The FIFO (30) buffers received data or data which are to be transmittedand effects decoupling in respect of time of the processes in thetransceiver chip and the external microcontroller.

The MAC State Machine (31) controls analogue and digital blocks inaccordance with the respective access method used (CSMA/CA, TDMA), itcontrols the implementation of the transmission and reception processesand it evaluates items of received protocol information (packet type,automatic target address comparison, ascertaining packet length and soforth).

The data which are to be transmitted or are received are processed inthe digital bit processing unit (32) (frame synchronisation, check sumgeneration and control, forward error correction,scrambling/unscrambling, optionally encrypting/decrypting).

The symbols received by the analogue part are detected by the bitdetector (33) and bit synchronisation is effected.

The power management (34) switches off external and internal powersupplies (power saving mode) and switches them on again controlled byinternal events (wake-up timer, battery management).

The microcontroller management (35) deactivates the power supply as wellas all connections to the external microcontroller. After the powersupply is switched on by the power management the start-up of themicrocontroller is controlled here.

The real time clock (36) includes a real time clock which is used forcontrolling the access process (TDMA) and the power saving mode. It alsoserves for time detection for applications. The wake-up timer stores themoment in time for leaving the power saving mode for the powermanagement.

The analogue blocks of the transceiver are controlled or interrogated byway of the control registers (37). The DiIOs (digital input/output)represent a digital sensor-actuator interface.

Hitherto suitable external SAW (Surface Acoustic Wave) components haveusually been employed for receiving chirp signals. The present inventionalso makes it possible to implement chirp signal reception and detectionthereof without corresponding external SAW components.

In that respect FIG. 15 shows that the chirp signal goes upon receptionafter passing through a differential comparator and the received signalis processed in a shift register connected to a suitable exclusive orinterlaced reference shift register.

In that way an upchirp signal and also a downchirp signal can be clearlydetected at the output side.

The use of the output correlator according to the invention means thatit is possible to forego an external SAW component—FIG. 16—, which makesthe receiver very advantageous and simple.

Insofar as the identification DDDL is used in the Figures, this is a‘Digital Differential Dispersive Line’.

The invention is not restricted solely to the disclosed transceiver butchirp signal reception as is disclosed in FIGS. 15 and 16 can also beimplemented independently of the transmitting unit of the transceiver.

The above-described transceiver can operate in the ISM band at about 2.4GHz. In that case for each transmitted symbol a chirp pulse of a bandwidth of 80 MHz is emitted (with an employed roll-off factor of 0.25,this results in an effective band width of 64 MHz). Accordingly thetransceiver system is a true wide-band system with all requiredproperties such as for example independence in relation to sources ofnoise.

In the receiver the energy which is distributed over the wide frequencyrange of 80 MHz is ‘collected in’ again so that the result is a veryshort and high pulse (sin x/x-function). For that purpose either anexternal SAW filter (surface acoustic wave) can be used in the receiver,or the solution as described with reference to FIGS. 15 and 16, so thatonly those energy parts which belong to the chirp pulse are ‘stacked oneupon the other’, while all others (for example noise and interferencesignals) pass the filter. As a result the actual signal stands outclearly from the background. That ‘system gain’ can be freely selectedwithin wide limits by increasing or reducing the length of the chirppulse. In the above-described process a chirp pulse duration of 1 μsecand an effective band width of 64 MHz (at 18 dB) are sufficient.

With the above-described process and the corresponding transceiver, evenat relatively high frequencies of 1.4 GHz, a range of 700 m in the openand more than 50 m in buildings (in each case with a transmission powerof 10 mW, the upper limit in the ISM band), is possible. The availablechannel resource is almost 100% utilised.

At the same time the system requires extremely little current, about 5mA in initial operation and 33 mA when transmitting 10 mW. The reasonfor this is substantially analogue signal processing which managesentirely without expensive digital signal processors for echosuppression.

Even less however is a low level of power consumption in the rest timesof the network (sleep mode) as generally data are transmitted onlyhighly sporadically. Here the system with a current of less than one μAis already at the limit of what is physically possible. That also makesit possible to achieve battery operating times of several years (thebattery can be disposed in the transceiver).

The described transceiver chip can be embodied using silicon-germaniumtechnology, but also using CMOS technology.

The particular application options of the described transceiver involvefactory automation, for example for monitoring machines. In addition agood field of application is intelligent access control with wirelesskeys (for example chip cards, active RFID), in order to wirelesslyidentify people, animals or goods. In comparison with passive systemsthe active RFID logistic tags have a greater range and in addition canalso be re-programmed. The use for alarm systems is also highlysuitable, in particular including alarm systems for fire or movement,and in that respect a bidirectional communication is possible between atransceiver and a corresponding chirp sensor. Use is also possible fornetworking computers, for example networking between a personal computerand a PDA or between a personal computer and the peripherals (mouse,keyboard).

As shown in FIG. 15 the DDDL comprises an input shift register whichreceives the output signal of a differential comparator. Each cell ofthe input shift register is linked to an exclusive OR unit which isfurther connected to the output of a memory which contains a storedreference for an upchirp signal and/or a stored sequence of a downchirpsignal. The individual results of the plurality of exclusive OR unitsare summed and made available to the correlator output. The sum resultis processed in a comparator component for ‘UP’ or ‘DOWN’ and then thecorresponding chirp signal is detected at the output of the comparatorand the result is made available. Besides the output of the correlatoroutput signal the comparator also receives a threshold signal anddelivers at the output a chirp-detected signal if the comparison resultbetween the correlator output signal and the threshold signal can becorrespondingly detected.

1. A transceiver of a transmission system having a device for producinga chirp signal, wherein there is provided a memory (RAM, ROM) in whichis stored a plurality of different chirp sequences which respectivelycorrespond individually or in pairs to a predetermined chirp signal,wherein upon call a desired individual chirp sequence or a pair of chirpsequences is read out of the memory and a predetermined chirp signal isproduced by means of the producing device which preferably singly or inpairs has the combination of a digital/analogue converter and a low passmember.
 2. A transceiver as set forth in claim 1 wherein, the chirpsequences stored in the memory can be sampled and bit-quantized chirpsignals in the baseband, in the original frequency position or in the IFposition, wherein bit quantization can be freely selected in the rangeof 1 . . . n.
 3. A transceiver as set forth in claim 2 wherein, thechirp signal (which can be any one) can be produced without acorresponding chirp filter, wherein outputted at the output of theproducing device are two signals I and Q which correspond to the realpart and the imaginary part of the predetermined chirp signal in thebaseband.
 4. A transceiver as set forth in claim 2 wherein outputted atthe output of the producing device is a signal which corresponds to thepredetermined chirp signal in the transmission frequency position.
 5. Atransceiver as set forth in claim 2 wherein outputted at the output ofthe producing device is a signal which corresponds to the predeterminedchirp signal in the intermediate frequency position.
 6. A transceiver asset forth in claim 2 wherein, for data transmission convolution pulses,that is to say combination signals comprise upchirp pulses and downchirppulses, are used, this involving purely real signals so that only onesingle chirp sequence has to be stored in the memory for therepresentation thereof in the baseband.
 7. A transceiver as set forth inclaim 3 wherein the output signals I and Q of the producing device areconverted into the transmission frequency band by means of an I/Qmodulator.
 8. A transceiver as set forth in claim 5 wherein the outputsignal of the producing device is converted from the IF position intothe transmission band by means of a modulation device (for example amixer, a modulator or a simple multiplier).
 9. A transceiver as setforth in claim 6 wherein the convolution pulse baseband signal at theoutput of the producing device is impressed on a real carrier signal bymeans of a single modulation member (for example a mixer, a modulator ora simple multiplier) and thereby converted into the transmissionfrequency band.
 10. A transceiver as set forth in claim 1 wherein chirpsignals of a differing BT-product and/or a differing time-frequencycharacteristic are stored in the memory and can be called up therefrom.11. A transceiver as set forth in claim 10 wherein it is possible tohave recourse to different ones of the stored chirp sequences independence on the transmission requirements.
 12. A transceiver as setforth in claim 10 wherein switching-over to other chirp sequences cantake place during ongoing transmission.
 13. A transceiver as set forthin claim 1 wherein the required chirp sequences in a process of startingup operation or initialisation are transferred into the memory of thetransceiver by download and if required can also be replaced byre-programming.
 14. A transceiver as set forth in claim 2 wherein thesampled chirp signals are additionally weighted with selectable filterfunctions (for example with a cosine roll-off characteristic) prior toquantization and storage in the memory.
 15. A transceiver as set forthin claim 1 wherein the chirp signals which come in at the receiver endare compressed with suitable dispersive filters in the carrier frequencyband and are then directly and asynchronously demodulated into thebaseband.
 16. A transceiver as set forth in claim 1 wherein the chirpsignals coming in at the receiver end are firstly converted into theintermediate frequency position, then compressed with suitabledispersive filters into the IF position and then asynchronouslydemodulated into the baseband.
 17. A transceiver as set forth in claim 1wherein the receiver device can be tuned(=programmed) to the chirpsignal used at the transmitter end by simple exchange of the dispersivefilters used while retaining all other receiver components.
 18. Atransceiver, in particular as set forth in claim 1, for producing,emitting and receiving convolution signals, wherein the convolutionsignals are compressed at the receiver end in the carrier frequencyposition by means of complementary dispersive delay lines anddemodulated directly and asynchronously into the baseband bymultiplication of the output signals of both delay lines.
 19. Atransceiver as set forth in claim 1, for producing, emitting andreceiving convolution signals, wherein the convolution signals arefirstly converted at the receiver end into the intermediate frequencyposition, compressed by means of complementary dispersive delay linesand demodulated asynchronously into the baseband by multiplication ofthe output signals of both delay lines.
 20. A transceiver as set forthin claim 19 wherein the congruence in respect of time of the envelopecurves of the two compressed signals is used as a criterion forcoincidence of the IF center frequency and the center frequency of thecomplementary dispersive filters in order to tune the local oscillatorof the receiving device in a phase regulating circuit.
 21. A transceiveras set forth in claim 19 wherein the output signals of the complementarydispersive delay lines are firstly passed to an envelope curve detectorwith subsequent threshold value comparator and the output signals of thethreshold value comparators are passed to a phase detector whose outputsignal reflects the displacement in respect of time of the two envelopecurves in respect of amount and polarity.
 22. A transceiver as set forthin claim 21 wherein the output signal of the phase detector is passed toa regulator which changes the setting voltage of a voltage-controlledoscillator (VCO) for producing the local oscillator (LO) at the receiverend, until both envelope curves are congruent.
 23. A transceiver as setforth in claim 1 wherein the received signal is synchronised to thecenter frequency of the complementary dispersive group transit timefilters.
 24. A transceiver as set forth in claim 1 wherein the phaseregulating circuit also regulates out changes in the center frequency ofthe dispersive filters, which were produced by a rise in temperature,ageing or other influences.
 25. A transceiver as set forth in claim 1for burst-wise transmission of data sequences by means of convolutionpulses, wherein a data sequence to be transmitted is preceded by apreamble comprising convolution pulses, which serves specifically forbringing frequency regulation into effect.
 26. A transceiver as setforth in claim 25 wherein upon the attainment of the steady-statecondition of frequency regulation the VCO setting voltage is sampledwith a sample-and-hold member and is held fast for the duration of adata burst.
 27. A transceiver as set forth in claim 1 for burst-wisetransmission of upchirp/downchirp pulses, wherein a data sequence to betransmitted is preceded by a preamble comprising convolution pulses,which serves specifically for bringing frequency regulation into effectand upon the attainment of the steady-state condition of frequencyregulation the VCO setting voltage is sampled with a sample-and-holdmember and is held fast for the duration of a data burst.
 28. Atransceiver as set forth in claim 1 for automatic frequency regulationin a system for burst-wise transmission of upchirp/downchirp pulses,wherein a data sequence is preceded in a preamble by a series ofmutually alternate upchirp and downchirp pulses and the phase regulatingcircuit as shown in FIG. 3 regulates not to a condition of congruence ofthe envelope curves but to a phase displacement of 180° and upon theattainment of the steady-state condition of frequency regulation the VCOsetting voltage is sampled with a sample-and-hold member and is heldfast for the duration of a data burst.
 29. A transceiver as set forth inclaim 28 wherein the phase detector is adapted to be switched over forreceiving convolution pulses or upchirp/downchirp pulses.
 30. Atransceiver as set forth in claim 1 with frequency regulation forreceiving upchirp/downchirp pulses, wherein an uninterrupted sequence ofsymbols which is the same as the detected symbols of a convolution pulsesequence is produced in both branches which adjoin the dispersivefilters by the insertion of dummy symbols so that a subsequent phasedetector can effect checking in respect of congruence of the envelopecurves and the regulating circuit shown in FIG. 4 can also be used forfrequency regulation of an upchirp/downchirp system.
 31. A transceiveras set forth in claim 30 wherein the symbol sequences produced at thetransmitter end are suitably scrambled prior to transmission, with theaim that the number of successive symbols of the same polarity does notexceed a specified value.
 32. A transceiver as set forth in claim 1wherein the chirp signals which are received in the receiver are firstlyconverted into the IF position, compressed in complementary dispersivedelay lines, then demodulated into the baseband with envelope curvedetectors and converted with threshold value comparators into digitallyprocessible signals and a logic EXCLUSIVE OR gate is used for derivingthe symbol clock, said gate linking the output signals of the thresholdvalue detectors, while a JK flip-flop is used for representation of thecurrent datum, the inputs J and K thereof being connected to the outputsof the threshold value detectors and the clock input thereof beingactuated with the output signal of the EXCLUSIVE OR gate.
 33. Atransceiver as set forth in claim 1 for receiving convolution pulses,wherein the chirp signals which are received in the receiver are firstlyconverted into the IF position and compressed in complementarydispersive delay lines and the output signals of the delay lines aremultiplied together and the output signal of the multiplier is subjectedto full-wave rectification and then passed to a threshold valuecomparator, at the output of which there is the symbol clock.
 34. Atransceiver as set forth in claim 1 for receiving convolution pulses,wherein the chirp signals received in the receiver are firstly convertedinto the IF position and compressed in complementary dispersive delaylines, then demodulated into the baseband with envelope curve detectorsand converted into digitally processible signals with threshold valuecomparators, and the outputs of the threshold value comparators aresubjected to logical AND gating in order to derive the symbol clock. 35.A transceiver, in particular as set forth in claim 1 for receivingconvolution pulses, wherein the chirp signals received in the receiverare firstly converted into the IF position and compressed incomplementary dispersive delay lines, and the output signals of thedelay lines are multiplied together and the bipolar output signals ofthe multiplier are converted into digitally processible signals withsubsequent threshold value comparators, whereupon the output signals ofthe threshold value comparators are subjected to logical AND gating inorder to derive the symbol clock, while a JK flip-flop is used torepresent the current datum, the inputs J and K of which are connectedto the outputs of the threshold value detectors and the clock input ofwhich is actuated with the output signal of the OR gate.
 36. Atransceiver with clock derivation as set forth in claim 32 having agating device comprising a switch and a time control which operates insuch a way that a symbol clock pulse entering at the input end isrecognised by the time control and causes opening of the switch for theduration of a specified blocking interval which is shorter than a symbolclock period, whereby interference pulses which occur within the symbolinterval are suppressed while the next following symbol clock pulse canagain pass and can again trigger off the procedure.
 37. A transceiver asset forth in claim 36 wherein a logic AND gate performs the function ofthe switch and a monoflop determines the length of the blockinginterval.
 38. A transceiver as set forth in claim 36 wherein the lengthof the blocking interval is variable and can be matched to thetransmission situation, for example to interference phenomena ontransmission.
 39. A transceiver as set forth in claim 38 wherein a shortblocking interval is used for the phase of bringing the receiving systeminto operation while the arrangement switches over to a longer blockinginterval in the steady-state condition.
 40. A transceiver as set forthin claim 36 wherein the gate, triggered by a symbol clock pulse, closesfor the duration of a blocking interval, then opens for the duration ofan opening interval (within which the next symbol clock pulse isexpected) and then closes again for the duration of a blocking interval,and that process is continuously repeated.
 41. A transceiver, inparticular as set forth in claim 1, wherein the chirp signals receivedin the receiver are firstly converted into the IF position, compressedin complementary dispersive delay lines, and then the compressed signalsare passed in both branches to a respective envelope curve detector, anaverage value detector and a peak value detector, wherein indownstream-connected threshold value comparators the output signal ofthe respective envelope curve detector is compared to a threshold valuewhich can variably assume a value between the average value and the peakvalue of the detected signal.
 42. A transceiver as set forth in claim 41wherein in both branches the position of the threshold value can bedigitally controlled between the signal average value and the signalpeak value.
 43. A transceiver as set forth in claim 42 wherein in bothbranches a voltage is added to the threshold value formed from thesignal average value and the signal peak value, thereby providing thatthe threshold value at the comparator input is always higher than thenoise amplitude at the output of the envelope curve detector.